The scope of this paper deals with issues regarding multiple clock designs and provides short but comprehensive information on the same. Designs involving single clock are like a walk in the park… but the real challenge comes when one has to face more than one clock. Designers are faced with problems of metastability, phase or frequency difference among the clocks involved, performing asynchronous data transfer, etc. This paper covers the issue of multiple clock domains & its problems, by starting with a simple design of a single clock FIFO and later expanding it to dual clock domain and separately detailing on the problems involving more than single clock domains. In short, this paper covers what all a designer needs to make a robust and efficient design involving multiple clock domains.