Need for Watchdog for improved system fault tolerance?→

Embedded electronic control units are finding their way into more and more complex safety critical and mission critical applications. Many of these applications operate in adverse conditions, which can cause code runaway in the embedded control units, putting them into unknown states. A watchdog timer is the best way to bring the system out of an unknown state into a safe state. Given its importance, the watchdog has to be carefully designed, so as to reduce the chances of its operation being compromised by runaway code. This paper outlines the need for robust Watchdog and the guidelines that must be considered while designing a fault tolerant system monitor aka Watchdog. New methods for refreshing a watchdog, write protection mechanism, early detection of code runaway and a quick self-test of the watchdog have been described herein.

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Ultra Low Power Designs Using Asynchronous Design Techniques (Welcome to the World Without Clocks)

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore's Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around 28.7 GHz. Essentially bus-based interconnects are being stretched to the point where they cannot be scaled further. This paper presents challenges with the synchronous (clocked) designs and describes the techniques to overcoming the same with asynchronous (Clockless) design methodology. The paper proposes to redesign the synchronous interconnect to an asynchronous interconnect that should cater to tomorrow's needs of high speed and low power. These circuits work on Handshaking techniques. If not today SOC industry will be forced driven to this methodology tomorrow.

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