System for preventing tampering with integrated circuit→

/ USPTO #8,896,086/

A tamper detector has input and output pins for connection to ends of a tamper detection circuit, and a corresponding set of linear feedback shift registers (LFSRs) timed by clock signals for generating pseudo-random coded detection signals as a function of seed values and of a generator polynomial defined by feedback taps. A comparator compares signals received from the detection circuit with the coded detection signals. A multiplexer provides the coded detection signal selectively from the LFSRs to the output pin and the comparator. A controller varies the seed values for different cycles of values of the pseudo-random coded detection signals. The controller also controls the generator polynomial and a frequency of the clock signals for different cycles of values of the pseudo-random coded detection signals.

 

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Tamper detector for secure module→

/ USPTO #8689357/

A tamper detector has input and output pins for connection to ends of a tamper detection circuit, and a corresponding set of linear feedback shift registers (LFSRs) timed by clock signals for generating pseudo-random coded detection signals as a function of seed values and of a generator polynomial defined by feedback taps. A comparator compares signals received from the detection circuit with the coded detection signals. A multiplexer provides the coded detection signal selectively from the LFSRs to the output pin and the comparator. A controller varies the seed values for different cycles of values of the pseudo-random coded detection signals. The controller also controls the generator polynomial and a frequency of the clock signals for different cycles of values of the pseudo-random coded detection signals.

 

System for compensating for variations in clock signal frequency→

/ USPTO #US8643410 B1/

A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.

 

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